Data processing system

ABSTRACT

A data processing system with improved data transfer capabilities. All units in the system including a random access memory unit, are connected in parallel. Data is transferred between any two units asynchronously with respect to a processor unit which normally controls the system. Other units can obtain system control by making a request which is honored if it has sufficient priority. Transfers requiring processor unit operation are made after an instruction is processed and may divert the processor unit to an interruption routine. Other transfers can be made whenever another unit in the system is not making a transfer. System control is returned to the processor unit or another peripheral unit when the data transfer is completed. If an interruption routine is to be executed, control is returned to the processor directly. Data transfers are controlled by synchronization signals from the controlling peripheral unit and the other unit involved in the transfer.

0 United States Patent m1 on 3,815,099 Cohen et al. 1 June 4, 1974 [54] DATA PROCESSING SYSTEM 3.710324 M973 Cohen 6! al. 340N715 [75] Inventors: John B. Cohen, West Acton; Paul E.

Janson, Boston, both of Mass; u nary [Hammer-Paul .l. Henon Ham L. McFarland, Jr" Santa Assistant Exammer-lan E. Rhoads I Clara Calm; James K Young, Jr" Arlorne Agent, or Fzrm--Cesari and McKenna Carlisle, Mass.

[73] Assignee: Digital Equipment Corporation, [57] ABSTRACT Maynard, Mass. A data processing system with improved data transfer capabilities. All units in the system including a random 22] Sept 1972 access memory unit, are connected in parallel, Data is [21] Appl. No.: 290,644 transferred between any two units asynchronously with respect to a processor unit which normally con- Relaed Apphcanon Data trols the system. Other units can obtain system control [62] Division of Ser. No. 24.636. April I, I970, Pat. No. by making a request which is hunored if has ff. cicnt priority. Transfers requiring processor unit operation are made after an instruction is processed and [5 Us. Cl. a. 340/1725 may divert h processor unit to an interruption row [5 I Int. Cl 006i 3/04, oosr l3/(l0 [incl other transfers can be made whenever another H8 new of Search 340M725 235/152 unit in the system is not making a transfer. System control is returned to the processor unit or another [56] References peripheral unit when the data transfer is completed. If

UNITED STATES PATENTS an interruption routine is to be executed, control is re- 3.48(J.9l4 ll/l969 Schlaeppi 340N725 turned to the processor directly. Data transfers are 3,512.!36 5/1970 Harmon et al 340N725 controlled by synchronization signals from the con- 3.5f 6.3fi3 2/l 7l Driscoll r v 340/1715 trolling peripheral unit and the other unit involved in 3.593.300 7/l97l Driscoll ct al. i. 34(l/l72.5 h transfer 3,b|4,74l) ill/I97] Delagi et al 340/1725 3.614.741 Ill/i971 McFarland et ul, 340/1715 10 Claims, 21 Drawing Figures 5 enocssson l a l CONT CONTROL SCTION SECTIW "an" urr N 2 um I 26 D-OATA A-ADDRm BR BUS REQUEST BG BUS GRANT NPR NON -PROCESSOR REQUEST CONTROL NPG-NON-PROCESSOR GRANT PROCESSOR SACK SELECTION ACKNOWLEDGEMENT MSYN MASTER SYNCHRONIZATION SSYN SLAVE SYNCHRONlZATION UNIT PATENTEDJUN 4 m4 SHKU 01 0F 19 so 1! J PROCESSOR UNT N CONTROL SECTION PERIPHERAL CONTROL SECTION PERIPHERAL UNT I CONTROL SECTION CONTROL FIG.|

D DATA Q A-ADDRESS BR BUS REQUEST 1 8G BUS GRANT NPR NON PROCESSOR REQUEST NPG NON PROCESSOR GRANT SACK SELECTION ACKNOWLEDGEMENT SSYN SLAVE SYNCHRON'ZATION FIG. 5

UNIT

PROCESSOR UNIT PATENTEB 4 I974 24 MEMORY UNIT saw 03 or 19 SUBRO T I SUBROUTINE SP-n 1 INSTRUCTIONS T SUBROUTINE 2 ii SUBROUTINE n SP-l FIG. 3

PATENTEIIJUII 4mm $815099 sum as 0T 19 BSR'I TRANSFER THE PC REGISTER CONTENTS TO THE B INPUT CIRCUIT 52 BSR'Z TRANSFER THE 8 INPUT CIRCUIT CONTENTS TO THE BUS ADDRESS REGISTER 34; THEN INCREMENT THE OUTPUT FROM THE ADDER UNIT 46 DATI BsR-a TRANSFER THE INCREMENTED OUTPUT FROM THE ADDER UNIT 46 TO THE PC REGISTER; TRANSFER THE INSTRUCTION FROM LOCATION DESIGNATED BY THE BUS ADDRESS REGISTER 34.

DECODE THE INSTRUCTION IN THE I INSTRUCTION DECODER 64.

DOES THE INSTRUCTION DECODE YES AS A "HALT" INSTRUCTION? Iwo MAY THE INSTRUCTION BE EXECUTED YES IMMEDIATELY INO DOES THE INSTRUCTION HAVE TWO No OPERAND ADDRESSES WITH THE FIRST HAVING A NONZERO ADDRESS MODE? YES USE THE FIRST OPERAND ADDRESS AS A DESIGNATED ADDRESS USE THE SINGLE OPERAND OR SECOND OPERAND ADDRESS AS A DESIGNATED ADDRESS BSRI TRANSFER THE CONTENTS OF THE DESIGNATED REGISTER TO THE B INPUT CIRCUIT 52; FOR MODE '4 OR'S OPERAND ADDRESSES, TRANSFER A DECREMENTING VALUE TO THE A INPUT CIRCUIT4B.

asR-2 TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34-, IF I THE ADDRESS IS MODE -2 0R -3, 0R TRANSFER AN INCREMENTING VALUE To DAT? THE A INPUT CIRCUIT 4s BSR'S TRANSFER THE ADDER UNIT OUTPUT TO THE SELECTED REGISTER; TRANSFER THE CONTENTS OF THE LOCATION ADDRESSED BY THE BUS ADDRESS 6) REGISTER 34 TO THE B INPUT CIRCUIT 52.

FIG. 6A

PAIENTEIIJUII 4 m4 slelslose B DoEs THE FIRST OPERAND (I? ADDRESS HAVE A MODE -I, YES -2, 0R -4 OPERAND ADDREss I NO BSR-I IF ADDREss MODE 6 0R '7, TRANSFER DESIGNATED REGISTER coNTENTs To THE A INPUT CIRCUIT 48 ADD INDEX VALUE IN THE B INPUT cIRcuIT 52 IF oTHER'MoDE,

NO oPERATIbN.

|$R 2 BSR'Z TRANSFER THE ADDER UNIT OUTPUT DATI OR TO THE BUS ADDRESS REGISTER 34. DAT|P BSR'3 TRANSFER THE CONTENTS OF THE LOCATION ADDRESSED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52 BSR '2 TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34.

( DOES THE FIRST OPERAND asR-3 TRANSFER THE CONTENTS DATI 0R OF THE LOCATION ADDREssED BY THE BUS DATIP ADDREss REGISTER 34 TO THE B INPUT CIRCUIT 52 NO IS THE OPERAND ADDRESS THE FIRST OF TWO IN THE INSTRUCTION? YES FIG. 6B

PATENTEDJUH 4mm 3815099 saw our 19 IS THE INSTRUCUON DECODED AS Y S A JMP TRANSFER INSTRUCTlON? TRANSFER THE ADDRESS DEFINED BY THE INSTRUCTION OPERAND ADDRESS TO THE PC REGISTER YES THE INSTRUCTlON OPERAND ADDRESS TO THE TEMP REGISTER TRANSFER THE ADDRESS DEFINED BY l lsR-w FIG. 6C

PATENIEIIJIIII 4mm SQSlSLOSS sum uanr19 (IS THE INSTRUCTION DECODED As NO JSR INSTRUCTION YES BSR-I TRANSFER THE SP REGISTER OONTENTS TO THEB INPUT CIRCUIT 52 ANDA DECREMENTING VALUE TO THE A INPUT CIRCUIT 4a.

BsR-2 TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34.

BSR-3 TRANSFER THE ADDER UNIT OUTPUT TO THE SP REGISTER.

ISR- O BSRO TRANSFER THE R5 REGISTER CONTENTS DATO TO THE 8 INPUT CIRCUIT 52.

BSRS TRANSFER THE ADDER UNIT OUTPUT ONTO THE BUS 30 FOR STORAGE AT THE LOCATION IDENTIFIED BY THE BUS ADDRESS REGISTER CONTENTS.

BSR-T WAIT FOR ACKNOWLEDGEMENT THAT THE R5 REGISTER CONTENTS ARE STORED.

TRANSFER THE PC REGISTER CONTENTS TO THE B INPUT CIRCUIT 52.

TRANSFER THE CONTENTS OF THE 2 ADDER UNIT TO THE R5 REGISTER.

TRANSFER THE CONTENTS OF THE TEMP ISR 3 REGISTER IN THE REGISTER MEM ORY 40 TO THE 8 INPUT CIRCUIT 52.

TRANSFER THE CONTENTS OF THE ADDER ISR- 4 UNIT TO THE PC REGISTER IN THE REGISTER MEMORY 40.

IS THE INSTRUCTION DECODED AS 0 A RTS INSTRUCTION FIG. 7A

PAIENIEIIJIJII 4 I974 ISR-4 ISR-G DATI ISR-T ISR-4 DATI saw us0r19 TRANSFER THE R5 REGISTER CONTENTS TO THE 8 INPUT CIRCUIT 52.

TRANSFER THE ADDER UNIT OUTPUT TO THE PC REGISTER IN THE REGISTER MEMORY 4O BSR-I BSR-3 TRANSFER THE ADDER UNIT OUTPUT TO THE R5 REGISTER IN THE REGISTER MEMORY 40.

IS THE INSTRUCTION DECODED AS A RTI INSTRUCTION Ives BSR-I BSR -2 BSR-3 TRANSFER THE CONTENTS OF THE SP REGISTER IN THE REGISTER MEMORY 40 TO THE B INPUT CIRCUIT 52.

TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34-,TRANS- FER AN INCREMENTING VALUE TO THE A INPUT CIRCUIT 48 TRANSFER THE' INCREMENTED VALUE FROM THE ADDER UNIT 46 TO THE SP REGISTER IN THE REGISTER MEMORY 40, TRANSFER THE CONTENTS OF THE LOCATION DEFINED BY THE BUS ADDRESS REGISTER 34 TO B INPUT CIRCUIT 52 FIG. 7B

PATENTEIJJIIN mm 3315099 SHEET '10 0F 19 |sR 5 TRANSFER THE ADDER UNIT OUTPUT TO THE PC REGISTER IN THE REGISTER MEMORY 40.

BSR-I TRANSFER THE CONTENTS THE SP REG.

ISTER IN THE REGISTER MEMORY 40 TO THE B INPUT CIRCUIT 52. BSR-2 TRANSFER THE ADDER UNIT OUTPUT TO THE BUS ADDRESS REGISTER 34 sR 6 TRANSFER AN INCREMENTING VALUE TO THE DAT A INPUT CIRCUIT 48.

BSR-3 TRANSFER THE INCREMENTED VALUE FROM THE ADDER UNIT 46 TO THE SP REG- ISTER IN THE REGISTER MEMORY 40; TRANSFER THE CONTENTS OF THE LOCATION DEFINED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52.

lsR 7 TRANSFER THE ADDER UNIT OUTPUT TO THE STATUS REGISTER 59 IN THE PRIORITY CONTROL UNIT 58.

IS THE INSTRUCTION DECODED AS A )NO BRANCH INSTRUCTION TRANSFER THE CONTENTS OF THE PC REG- ISR-I lsTER IN THE REGISTER MEMORY 40 10 THE A INPUT CIR'CUIT48.

FIG. 7C

PAIENTEIJJUII 4 I9?- ISR-I ISR-Z ISR-S sum 11 0f 19 OES THE SECOND OPERAND ADDRESS IN A TWO OPERAND ADDRESS IN STRUCTION OR THE SINGLE OPERAND IN A SINGLE OPERAND ADDRESS INSTRUCTION HAVE A ZERO ADDRESS MODE YES TRANSFER THE CONTENTS OF THE LOCATION DEFINED BY THE OPERAND ADDRESS FROM THE SELECTED REG ISTER IN THE REGISTER MEMORY 40 TO ONE OF THE INPUT CIRCUITS 48 OR 52.

DOES THE INSTRUCTION HAVE TWO OPERAND ADDRESSES YES SOURCE REGISTER IN THE REGISTER TRANSFER THE CONTENTS OF THE MEMORY 40 TO THE OTHER LATCH DOES-THE m'smucflow RE OUlRE T RE-I NQWWU ADDITION OF CONSTANTS YES TRANSFER THE CONSTANT TO THE APPRO- PRIATE ONE OF INPUT CIRCUITS 48 OR 52.

IS THE INSTRUCTION DECODED AS A BIT OR A BIC INSTRUCTION YES TRANSFER THE CONTENTS OF THE ADDER UNIT 46 TO THE TEMP REGISTER IN THE REGISTER MEMORY 40.

TRANSFER THE TEMP REGISTER CONTENTS IN THE REGISTER MEMORY 40 TO THE A INPUT CIRCUIT 48.

FIG. 70

PATENTEU 4 I374 ISR-4 lSR-4 ISR-4 ISR-4 DATO ALTER THE CONDITION STATUS REGISTER 59 CODES IN THE IN THE STATUS UNIT 58.

I IS THE INSTRUCTION DECODED AS o A TST, BIT BIC OR CMP INSTRUCTION 9 YES 68 A STATUS WORD BEING CHANGED P) YES TRANSFER THE STATUS WORD TO THE MEMORY OPERANO ADDRESS HAVE A MODE- UNIT 24 FOR STORAGE.

DOES THE SECOND OR SINGLE OPERANO ADDRE SS YES BSR '6 BSR-T TRANSFER THE DATA FROM THE ADDER UNIT 40 DESIGNATED BY THE OPERAND ADDRESS.

THE REGISTER IN THE REGISTER MEMORII TRANSFER THE DATA FROM THE ADDER UNIT 46 TO THE BUS 30 FOR STORAGE AT THE LOCATION DEFINED BY THE BUS ADDRESS REGISTER CONTENTS WAIT FOR ACKNOWLEDGEMENT THAT THE DATA IS STORED IN THE ADDRESSED LOCATION.

TERM

FIG. 7E

PAIENTEUJIIII 4mm 3815099 SHEET 130F153 DO ANY BUS REQUEST SIGNALS FROM NO PRIORITY CONTROL UNIT 62 EXIST YEs PROcEssOR UNIT 22 RELINQUISHES OONTROI. OF BUS so DEPENDING UPON PRIORITY REQUESTING PERIPHERAL TRANSMITS AN SW AOOREss TO THE TEMP REOIsTER IN THE REGISTER MEMORY 40.

BSR-l TRANsFER THE sP REOIsTER cONTENTs TO THE 5 INPUT CIRCUIT s2 ANO A MORE- MENTINO QUANTITY TO A INPUT CIRCUIT48, BSR-2 TRANsFER THE AOOER UNIT OUTPUT TO THE BUS AOOREss REGISTER 34. BSR-3 TRANsFER THE AOOER UNIT OUTPUT TO 15R- 2 THE sP REOIsTERI BSR-4 NO OPERATION. DATO BSR-S TRANsFER THE sTATUs REGISTER cON TENTs FROM THE STATUS N T 50 TO THE BUS 3O BSR wAIT FOR ACKNOWLEDGEMENT THAT THE sTATUs wORO Is sTOREO IN THE MEMORY UNIT 24 AT THE LOCATION DEFINED BY THE BUS AOOREss REGISTER 34 BSR- I TRANSFER THE sP REGISTER cONTENTs TO THE 8 INPUT OIROUIT 56 AND A DECRE- MENTINO VALUE TO THE AINPUT CIRCUIT4 BSR-2 TRANSFER THE ADDER UNIT OUTPUT TO THE BUS AOOREss REOIsTER 34. BSR -a TRANsFER THE AOOER UNIT OUTPUT TO THE SP REGISTER. IsR- 3 esR-O TRANsFER PC REGISTER cONTENTs TO THE B INPUT CIRCUIT 52. To BSR -s TRANsFER THE E INPUT cIRcUIT cONTENTs TO THE BUS so. BSR-T WAIT FOR ACKNOWLEDGEMENT THAT THE PROGRAM COUNT IS STORED IN THE MEMORY UNIT 24 AT THE LOCATION OEFINEO BY THE BUS AOOREss REGISTER 54.

FIG. 8A

PATEIITEIIIIIII mm 18151099 SHEET 1% 0F 19 BSR-I TRANSFER THE TEMF? REGISTER CONTENTS TO THE 5 INPUT CIRCUIT 52v BSR-Z TRANSFER THE B INPUT CIRCUIT CONTENTS TO THE BUS ADDRESS REGISTER 34; INCREMENT THE 6 INPUT CIRCUIT CONTENTS BY TRANSFERRING AN ISR -4 INCREMENTING VALUE To THE A INPUT CIRCUIT s4 BSR-3 TRANSFER THE ADDER UNIT OUTPUT TO THE TEMP. REGISTER; TRANSFER THE CONTENTS OF THE LOCATION DEFINED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52.

5 TRANSFER THE 8 INPUT CIRCUIT CONTENTS TO THE PC REGISTER.

BSR-I TRANSFER THE TEMR REGISTER CON- TENTS TO THE B INPUT CIRCUIT 52. BSR -2 TRANSFER THE B INPUT CIRCUIT CONTENTS TO THE BUS ADDRESS REGISTER 34; INCREMENT THE 8 INPUT CIRCUIT CONTENTS BY TRANSFERRING AN INCREMENTING VALUE TO THE A INPUT CIRCUIT 48.

DAT BSR-3 TRANSFER THE ADDER UNIT OUTPUT TO THE TEMR REGISTER; TRANSFER THE CONTENTS OF THE LOCATION DEFINED BY THE BUS ADDRESS REGISTER 34 TO THE B INPUT CIRCUIT 52.

ISR-B TRANSFER THE INPUT CIRCUIT ISR- 7 CONTENTS TO THE STATUS REGISTER 59 IN THE STATUS UNIT 58.

F ETCH FIG. 8B

PATENTEDJUN 4 mm 38315099 sum 1s at 19 CLK \IlIlJlliJllL 5m m PESS' DTIZI3Q}|'2|3|1|]2'3l@ WRITE I F1 SHIFT REGISTER '2 3 4 STATE J T FIG. 9A

TsR-z INSTRUCT'ON THSR-T TIMING UNIT 66 17s SHIFT REGISTER l TlMINGSIGNAL 1 GENERATOR T TIMING r CIRCUIT aus SHIFT i REGISTER i SIGNAL GENERATORI i l 

1. A data unit adapted for connection to a multiple conductor bus in a data processing system, the data processing system having means for transmitting address signals, cycle control signals indicating the direction of a data transfer and a delayed first synchronization signal onto corresponding bus conductors to produce in said data unit at least one type of data unit cycle for transferring data between bus data conductors and said data unit during a transfer interval, said data unit comprising: A. at least one data storage location with each said location having a unique address, B. selection means for generating a data unit selection signal in response to address signals on the address conductors which identify any storage location in said data unit, C. means for performing a data unit cycle during a transfer interval, D. means connected to said data unit cycle performing means and responsive to the cycle control signals for controlling the type of data unit cycle that is performed, E. coincidence means connected to said data unit cycle performing means and responsive to the coincidence of a delayed first synchronization signal and a data unit selection signal to initiate a data unit cycle, and F. means responsive to said coincidence means for generating a second synchronization signal indicative of the completion of a data unit cycle and responsive to a subsequent termination of the delayed first synchronization signal for terminating the second synchronization signal.
 2. A data unit as recited in claim 1 comprising a sEt of data storage locations with an ordered sequence of addresses, said selection means additionally including an address decoder responsive to the address signals for selecting a specified one of said data storage location for the data unit cycle.
 3. A data unit as recited in claim 1 wherein said second synchronizing signal generating means includes a delay circuit responsive to the initiation of a data unit cycle by said coincidence means.
 4. A data unit as recited in claim 1 wherein said cycle control signals indicate a transfer into an identified one of said storage locations from the data conductors during the transfer interval, said second synchronization signal generating means producing the second synchronization signal to indicate the storage of the data in the identified location by said data unit cycle performing means.
 5. A data unit as recited in claim 1 wherein said cycle control signals indicate a transfer from an identified one of said locations onto the data conductors during the transfer interval, said second synchronization signal generating means producing the second synchronization signal to indicate that data from the identified location has been placed on the data conductors by said data unit cycle performing means.
 6. A peripheral unit adapted for controlling a data transfer with another unit in a data processing system in which the peripheral units have relative priorities in the system, the system including a priority element adapted for connection to a data processing system bus having data, address and control conductor means, said peripheral unit comprising: A. request means for transmitting a request signal onto request control conductor means when said peripheral unit is prepared to control a data transfer, B. acknowledgement means responsive to the coincidence of a request signal from said request means and the receipt of a granting signal from the priority element on a granting control conductor means by transmitting an acknowledgement signal onto an acknowledgement control conductor means, said request means terminating the request signal in response to the acknowledgement signal, C. interval indicating means responsive to the coincidence of an acknowledgement signal and the absence of a busy signal on a busy control conductor means by indicating an interval during which said peripheral unit can transfer data, D. busy signal generating means responsive to said interval indicating means for transmitting a busy signal onto the busy control conductor means, said acknowledgement signal transmitting means terminating the acknowledgement signal in response to the busy signal generating means, and E. means responsive to said busy signal generating means for controlling a data transfer over the data conductor means between the peripheral unit and another unit connected to the system bus, said busy signal generating means terminating the busy signal on completion of the data transfer operation to indicate the end of the data transfer interval.
 7. A peripheral unit as recited in claim 6 wherein said data transfer control means includes: i. means for generating address signals onto the address conductor means for another unit in the system, ii. means for generating cycle control signals onto cycle control conductor means indicating the direction of a data transfer, and iii. means for generating a delayed first synchronizing signal onto first synchronization control conductor means, the signal initiating a data unit cycle in the other unit to thereby effect the transfer during the data transfer interval.
 8. A peripheral unit as recited in claim 6 wherein the data processing system additionally comprises a processor unit connected to the system bus, said peripheral unit additionally including a circuit enabled in response to certain requests for effecting a transfer of data directly to the processor, said circuit comprising i. means for transmitting a digital word onto the data conDuctors, ii. means responsive to said busy signal generating means for transmitting an interruption signal onto interrupt control conductor means, the processor unit accepting the digital word in response to the interrupt signal and sending a second synchronization signal onto second synchronization control conductor means for indicating the receipt of the digital word, and iii. means responsive to the second synchronization signal for disabling said interruption signal transmitting means, said digital word transmitting means and said busy signal generating means.
 9. A peripheral unit as recited in claim 6 additionally comprising: A. non-processor request means for transmitting a non-processor request onto non-processor request control conductor means, and B. means responsive to said non-processor request means and to a signal granting the non-processor request appearing on non-processor granting control conductor means for enabling said acknowledgement means, said busy signal generating means and said data transfer control means to effect a data transfer with another unit connected to the bus, said data transfer control means including means for transmitting address signals onto the address conductor means to identify the other unit to be involved in the transfer.
 10. A peripheral unit as recited in claim 9 wherein said data transfer control means additionally comprises: A. means for transmitting a delayed first synchronization signal onto first synchronization control conductor means indicating the initiation of a data transfer cycle, the other unit including means for effecting a data unit cycle in response thereto and generating a second synchronization signal onto second synchronization control conductor means indicating the completion of the data unit cycle, B. means responsive to the receipt of the second synchronization signal disabling said delayed first synchronization transmitting means, the other unit thereby terminating its second synchronization signal, and C. means responsive to the termination of the second synchronization signal for disabling said busy signal generating means to thereby terminate the data transfer interval. 